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What’s New in Xilinx ISE Design Suite 13.1
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Ability to create a new System Generator source in Project Navigator
Ability to create a new System Generator source in Project Navigator
Support for viewing TWR reports in Timing Analyzer
PlanAhead
ISE Simulator Integration
PlanAhead release 13 has integrated the Xilinx? ISE Simulator (ISim), into the design flow.
This new integration enables development and verification of designs completely within
the PlanAhead user interface. PlanAhead now has support for simulation-only sources
added to the project, which is performed either in the new project wizard or in the add
sources dialog. The Flow Navigator provides access to ISE Simulator.
You can invoke ISim:
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After RTL Design for behavioral simulation
After Implementation for timing simulation
Hierarchical Design Methodology Support
PlanAhead release 13 supports the Hierarchical Design features as described in the
following subsections.
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Incremental XST flow in RTL projects
Importing a partition into a different hierarchy than the one in which the partition
was created in the ISE Simulator
AREA_GROUPS within partitions
Black Box support in Synthesis and Implementation
Boundary optimization for constants and unconnected inputs and outputs on
partition ports.
Defining partitions for Design Preservation in Netlist-based projects.
Team Based Design Support
PlanAhead 13 adds support for new team-based design methodology. Team based design
supports multiple engineers implementing at a module level within a design to work in
parallel. The flow then supports assembling the module level runs by a team leader at the
top level with support for preservation levels to control the placement and routing
information that is kept during import.
See the Hierarchical Design Methodology Guide (UG748) and Chapter 13, Hierarchical Design
Techniques, in the PlanAhead User Guide (UG632) for more information.
Design Preservation RTL Support
PlanAhead 13 enhances support for design preservation flows by adding incremental
compilation for RTL synthesis of partitions with XST. The design preservation flow allows
a designer to mark portions of a design to be preserved in subsequent iterations and
enabled incremental compilation. In prior releases, design preservation was only
supported post synthesis. RTL-level control was added to provide designers an easier to
use flow to control partitions throughout the design flow from synthesis through
implementation within the PlanAhead user interface.
See the Hierarchical Design Methodology Guide (UG748) and Chapter 13, Hierarchical Design
Techniques, in the PlanAhead User Guide (UG632) for more information.
ISE Design Suite 13: Release Notes Guide
UG631 (v 13.1)
www.xilinx.com
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相关PDF资料
EF-EDK-FL SOFTWARE EDK EMBED FLOAT
EF-ISE-DSP-FL SOFTWARE ISE DSP EDITION
EF-ISE-SYSTEM-FL ISE DESIGN SYST FLOATING LICENSE
EF-VIVADO-HLS-FL VIVADO HLS, FLOATING LICENSE
EFM32-GXXX-PTB BOARD PROTOTYPING FOR EFM32
EFS315 FUSE INDUST 315A 415V BS IEC
EHBNCSCB CONN EH BNC T/H SOLDER CUP BLK
EHE004 BOARD ENERGY HARVESTING
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